SH7050 Datasheet, PDF (361/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timing of Prescaler Register (PSCR1), Timer Control Register (TCR), and Timer Mode
Register (TMDR) Setting: Settings in the prescaler register (PSCR1), timer control register
(TCR), and timer mode register (TMDR) should be made before the counter is started. Operation
is not guaranteed if these registers are modified while the counter is running.
Interrupt Status Flag Clearing Procedure: When an interrupt status flag is cleared to 0 by the
CPU, it must first be read before 0 is written to it. Correct operation cannot be guaranteed if 0 is
written without first reading the flag.
Setting H'0000 in Free-Running Counters 6 to 9 (TCNT6 to TCNT9): If H'0000 is written to a
channel 6 to 9 free-running counter (TCNT6 to TCNT9), and the counter is started, the interval up
to the first compare-match with the cycle register (CYLR) and duty register (DTR) will be a
maximum of one TCNT input clock cycle longer than the set value. With subsequent compare-
matches, the correct waveform will be output for the CYLR and DTR values.
Register Values when a Free-Running Counter (TCNT) Halts: If the timer start register
(TSTR) value is set to 0 during counter operation, only incrementing of the corresponding free-
running counter (TCNT) is stopped, and neither the free-running counter (TCNT) nor any other
ATU registers are initialized. The external output value at the time TSTR is cleared to 0 will
continue to be output.
TCNT0 Writing and Interval Timer Operation: If the CPU program writes 1 to a bit in free-
running counter 0 (TCNT0) corresponding to a bit set to 1 in the interval interrupt request register
(ITVRR) when that TCNT0 bit is 0, TCNT0 bit 10, 11, 12, or 13 will be detected as having
changed from 0 to 1, and an interrupt request will be sent to INTC and A/D sampling will be
started.
Automatic TSR Clearing by DMAC Activation by the ATU: When the DMAC is activated by
the ATU, automatic clearing of TSR will not be performed unless an address in the ATU’s I/O
space (H'FFFF8200 to H'FFFF82FF) is set as either the DMAC data transfer source address or
destination address. If it is wished to set an address outside the ATU’s I/O space for both transfer
source and destination, the corresponding bit should be written with 0 after being read while set to
1 from within the interrupt handling routine.
Interrupt Status Flag Setting/Resetting: With TSRF, a 0 write to a bit is invalid only if
duplicate events have occurred for the same bit before writing 0 after reading 1 to clear a specific
bit. (The duplicate events are accepted.) In order to perform the 0 write, another 1 read is
necessary. Also, with TSRA to TSRE, events are not accepted even if duplicate events have
occurred for the same bit before a 0 write following a 1 read is performed.
Rev. 5.00 Jan 06, 2006 page 341 of 818
REJ09B0273-0500