SH7050 Datasheet, PDF (184/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
2nd bus cycle
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The SAR value is taken as the address, memory data is read, and the value is stored in the
temporary buffer. Since the value read at this time is used as the address, it must be 32 bits.
3rd bus cycle
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The value in the temporary buffer is taken as the address, and data is read from the
transfer source module to the data buffer.
4th bus cycle
DMAC
SAR3
Memory
DAR3
Temporary
buffer
Data
buffer
Transfer source
module
Transfer destination
module
The DAR3 value is taken as the address, and the value in the data buffer is written to the
transfer destination module.
Note: Memory, transfer source, and transfer destination modules are shown here.
In practice, connection can be made anywhere there is address space.
Figure 9.9 Dual Address Mode and Indirect Address Operation
Rev. 5.00 Jan 06, 2006 page 164 of 818
REJ09B0273-0500