SH7050 Datasheet, PDF (158/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.1.3 Pin Configuration
Table 9.1 shows the DMAC pins.
Table 9.1 DMAC Pin Configuration
Channel Name
Symbol I/O
0
DMA transfer request DREQ0 I
DMA transfer request DACK0 O
acknowledge
DREQ0 acceptance
DRAK0
O
confirmation
1
DMA transfer request DREQ1 I
DMA transfer request DACK1 O
acknowledge
DREQ1 acceptance
DRAK1
O
confirmation
Function
DMA transfer request input from
external device to channel 0
DMA transfer strobe output from
channel 0 to external device
Sampling receive acknowledge output
for DMA transfer request input from
external source
DMA transfer request input from
external device to channel 1
DMA transfer strobe output from
channel 1 to external device
Sampling receive acknowledge output
for DMA transfer request input from
external source
9.1.4 Register Configuration
Table 9.2 summarizes the DMAC registers. DMAC has a total of 17 registers. Each channel has
four control registers. One other control register is shared by all channels. There are two channel 0
dedicated registers, ISAR and IDAR, which preserve different initial transfer source and
destination addresses than those of the SAR0 and DAR0. There is also an IAR used by the indirect
address mode.
Rev. 5.00 Jan 06, 2006 page 138 of 818
REJ09B0273-0500