SH7050 Datasheet, PDF (179/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.3.5 Address Modes
Single Address Mode: In the single address mode, both the transfer source and destination are
external; one (selectable) is accessed by a DACK signal while the other is accessed by an address.
In this mode, the DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a
transfer request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 9.5 shows a transfer between an external memory
and an external device with DACK in which the external device outputs data to the data bus while
that data is written in external memory in the same bus cycle.
External address bus External data bus
SuperH microcomputer
DMAC
External
memory
External device
with DACK
DACK
DREQ
: Data flow
Figure 9.5 Data Flow in Single Address Mode
Two types of transfers are possible in the single address mode: (a) transfers between external
devices with DACK and memory-mapped external devices, and (b) transfers between external
devices with DACK and external memory. The only transfer requests for either of these is the
external request (DREQ). Figure 9.6 shows the DMA transfer timing for the single address mode.
Rev. 5.00 Jan 06, 2006 page 159 of 818
REJ09B0273-0500