SH7050 Datasheet, PDF (315/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
TIA0
H'FFFFFFFF
Channel 0
counter
value
Data X1
Data X2
TCNT0
H'00000000
Channel 1
counter
value
TCNT1
H'FFFF
Data Y1
Data Y2
H'0000
ICR0AH/L
OSBR
Data X1
Data Y1
Time
Time
Data X2
Data Y2
Figure 10.19 Example of Twin-Capture Operation
10.3.9 PWM Timer Function
PWM mode is set unconditionally for ATU channels 6 to 9, and also by setting 1 in the
corresponding bit (T3PWM to T5PWM) of the ATU channel 3 to 5 timer mode registers (TMDR),
enabling the counters to be used as PWM timers.
In ATU channels 6 to 9, when the free-running counter (TCNT) is started, 0 is output to the
external pin if the corresponding duty register (DTR6 to DTR9) value is 0, and 1 is output to the
external pin if the DTR6 to DTR9 value is 1. When the TCNT count matches the DTR6 to DTR9
value after the up-count is started, 0 is output to the corresponding external pin (unless 100% duty
has been set, in which case 1 is output). When the continuing TCNT up-count matches the cycle
register (CYLR) value, 1 is output to the corresponding external pin (unless 0% duty has been set,
in which case 0 is output). At the same time, the counter is cleared. 0% duty is specified by setting
DTR to H'0000, and 100% duty by setting DTR ≥ CYLR.
The relationship between pins and registers is shown in table 10.4. Details of the buffer function
for ATU channels 6 to 9 are given in section 10.3.10, Buffer Function.
Rev. 5.00 Jan 06, 2006 page 295 of 818
REJ09B0273-0500