SH7050 Datasheet, PDF (174/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Table 9.4 Selecting On-Chip Peripheral Module Request Modes with the RS Bits
DMAC Transfer DMAC Transfer Transfer Transfer
RS3 RS2 RS1 RS0 Request Source Request Signal Source Destination Bus Mode
0 1 1 0 ATU
Compare-match Don’t care^* Don’t care^* Burst/cycle
6 generation
steal
1 ATU
Input capture B
generation
Don’t care^* Don’t care^* Burst/cycle
steal
1000
SCI0 transmit
block
TXI0 (SCI0
transmit-data-
empty transfer
request)
Don’t care^* TDR0
Burst/cycle
steal
1 SCI0 receive
block
RXI0 (SCI0
receive-data-full
transfer request)
RDR0
Don’t care^* Burst/cycle
steal
10
SCI1 transmit
block
TXI1 (SCI1
transmit-data-
empty transfer
request)
Don’t care^* TDR1
Burst/cycle
steal
1 SCI1 receive
block
RXI1 (SCI1
receive-data-full
transfer request)
RDR1
Don’t care^* Burst/cycle
steal
100
SCI2 transmit
block
TXI2 (SCI2
transmit-data-
empty transfer
request)
Don’t care^* TDR2
Burst/cycle
steal
1 SCI2 receive
block
RXI2 (SCI2
receive-data-full
transfer request)
RDR2
Don’t care^* Burst/cycle
steal
10
A/D converter
ADI (A/D
conversion end
interrupt)
ADDR0
Don’t care^* Burst/cycle
steal
1 A/D converter ADI (A/D
ADDR1 Don’t care^* Burst/cycle
conversion end
steal
interrupt)
ATU:
Advanced timer unit
SCI0, SCI1, SCI2: Serial communication interface channels 0–2
ADDR0, ADDR1: A/D converter channel 0 and 1 A/D registers
Note: * External memory, memory-mapped external device, on-chip memory, on-chip
peripheral module (excluding DMAC, BSC, and UBC)
Rev. 5.00 Jan 06, 2006 page 154 of 818
REJ09B0273-0500