SH7050 Datasheet, PDF (267/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 3—Input Capture/Compare-Match Flag (IMF4A): Status flag that indicates GR4A input
capture or compare-match.
Bit 3:
IMF4A
0
1
Description
[Clearing condition]
(Initial value)
When IMF4A is read while set to 1, then 0 is written in IMF4A
[Setting conditions]
• When the TCNT4 value is transferred to GR4A by an input capture signal while
GR4A is functioning as an input capture register
• When TCNT4 = GR4A while GR4A is functioning as an output compare register
Bit 2—Overflow Flag (OVF5): Status flag that indicates TCNT5 overflow.
Bit 2:
OVF5
0
1
Description
[Clearing condition]
When OVF5 is read while set to 1, then 0 is written in OVF5
[Setting condition]
When the TCNT5 value overflows (from H'FFFF to H'0000)
(Initial value)
Bit 1—Input Capture/Compare-Match Flag (IMF5B): Status flag that indicates GR5B input
capture or compare-match.
Bit 1:
IMF5B
0
1
Description
[Clearing condition]
(Initial value)
When IMF5B is read while set to 1, then 0 is written in IMF5B
[Setting conditions]
• When the TCNT5 value is transferred to GR5B by an input capture signal while
GR5B is functioning as an input capture register
• When TCNT5 = GR5B while GR5B is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 247 of 818
REJ09B0273-0500