SH7050 Datasheet, PDF (305/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
operation in response to a compare-match signal and outputting 1 to the external output pin, then
halting the count operation when DCNT underflows, and outputting 0.
Prescaler: The ATU has a dedicated prescaler with a 2-stage configuration. The first prescaler
stage includes a 5-bit prescaler register (PSCR1) that allows any scaling factor from 1 to 1/32 to
be specified. The first prescaler stage supplies a clock (φ') scaled from the φ clock second
prescaler stage and to channel 0. The second prescaler stage further scales the φ' clock supplied by
the first stage by a factor of the reciprocal of a power of 2 (the power being between 0 and 5) to
create six different clocks (φ") to be supplied to channels 1 to 10.
In channels 1 to 9, one of the six clocks (φ") created by scaling in the second prescaler stage can
be selected for use. In channel 10, two of the φ" clocks can be selected, with one clock input for
DCNT10A to DCNT10F, and the other for DCNT10G and DCNT10H.
10.3.2 Free-Running Count Operation and Cyclic Count Operation
The ATU channel 0 to 5 free-running counters (TCNT) are all designated as free-running counters
immediately after a reset, and start counting up as free-running counters when the corresponding
TSTR bit is set to 1. When TCNT overflows (channel 0: from H'FFFFFFFF to H'00000000;
channels 1 to 5: from H'FFFF to H'0000), the OVF bit in the timer status register (TSR) is set to 1.
If the OVE bit in the corresponding timer interrupt enable register (TIER) is set to 1 at this time,
an interrupt request is sent to the CPU. After overflowing, TCNT starts counting up again from
H'00000000 or H'0000.
If the timer start register (TSTR) value is cleared to 0 during the count, only the corresponding
free-running counter (TCNT) stops counting, and initialization of all TCNT counters and ATU
registers is not performed. The value at the point at which the TSTR value is cleared to 0
continues to be output externally.
Free-running counter operation is shown in figure 10.11.
(For channel 0: H'00000000 to H'FFFFFFFF)
H'FFFF
H'0000
STR bit
in TSTR
OVF
Time
Figure 10.11 Free-Running Counter Operation
Rev. 5.00 Jan 06, 2006 page 285 of 818
REJ09B0273-0500