SH7050 Datasheet, PDF (564/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
18.5 Register Descriptions
18.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by
setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase
mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting
the E bit. FLMCR1 is initialized by a reset, and in hardware standby mode and software standby
mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low
level is input. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
Writes to bits SWE, ESU, PSU, EV, and PV in FLMCR1 are enabled only when FWE = 1 and
SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit
only when FWE = 1, SWE = 1, and PSU = 1.
Bit: 7
6
5
4
3
2
1
0
FWE SWE ESU PSU
EV
PV
E
P
Initial value: 1/0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing.
Bit 7:
FWE
0
1
Description
When a low level is input to the FWE pin (hardware-protected state)
When a high level is input to the FWE pin
(Initial value)
Bit 6—Software Write Enable Bit (SWE): Enables or disables the flash memory. This bit should
be set before setting bits 5 to 0, and EBR1 bits 7 to 0.
Rev. 5.00 Jan 06, 2006 page 544 of 818
REJ09B0273-0500