SH7050 Datasheet, PDF (548/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.6.2 Port E Data Register (PEDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
—
PE14 PE13 PE12 PE11 PE10 PE9
DR DR DR DR DR DR
PE8
DR
PE7
DR
PE6
DR
PE5
DR
PE4
DR
PE3
DR
PE2
DR
PE1
DR
PE0
DR
Initial value: 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port E data register (PEDR) is a 16-bit readable/writable register that stores port E data. Bits
PE14DR to PE0DR correspond to pins PE14/TIOC3 to PE0/TIOA1.
When a pin functions as a general output, if a value is written to PEDR, that value is output
directly from the pin, and if PEDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PEDR is read the pin state, not the register value, is
returned directly. If a value is written to PEDR, although that value is written into PEDR it does
not affect the pin state. Table 17.10 summarizes port E data register read/write operations.
PEDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Table 17.10 Port E Data Register (PEDR) Read/Write Operations
PEIOR
0
1
Pin Function
General input
Other than general
input
General output
Other than general
output
Read
Pin state
Pin state
PEDR value
PEDR value
Write
Value is written to PEDR, but does not affect
pin state
Value is written to PEDR, but does not affect
pin state
Write value is output from pin
Value is written to PEDR, but does not affect
pin state
Rev. 5.00 Jan 06, 2006 page 528 of 818
REJ09B0273-0500