SH7050 Datasheet, PDF (226/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channels 6 to 9: Figure 10.7 shows a block diagram of ATU channels 6 to 9.
TSTR
Clock selection
Comparator
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Control logic
CMI6–9
TO6–9
Module data bus
Legend:
TCR: Timer control register (8 bits)
TSRE: Timer status register E (8 bits)
TIERE: Timer interrupt enable register E (8 bits)
TCNT: Free-running counter (16 bits)
CYLR: Cycle register (16 bits)
BFR: Buffer register (16 bits)
DTR: Duty register (16 bits)
Interrupt:
CMI: Cycle compare-match interrupt
Figure 10.7 Block Diagram of Channels 6 to 9
Rev. 5.00 Jan 06, 2006 page 206 of 818
REJ09B0273-0500