SH7050 Datasheet, PDF (592/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
Table 18.12 AC Characteristics in Transition to Memory Read Mode
Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, T_a = 25°C ±5°C
Item
Command write cycle
CE hold time
CE setup time
Data hold time
Data setup time
Write pulse width
WE rise time
WE fall time
Symbol
t_nxtc
t_ceh
t_ces
t_dh
t
ds
t
wep
t_r
t_f
Min
20
0
0
50
50
70
Max
Unit
µs
ns
ns
ns
ns
ns
30
ns
30
ns
Notes
A16–A0
CE
Command write
t_ces
t_ceh
t_nxtc
Memory read mode
Address stable
OE
WE
I/O7–I/O0
t_wep
t_f
t_r
t_ds
t_dh
Note: Data is latched on the rising edge of WE.
Figure 18.14 Timing Waveforms for Memory Read after Memory Write
Rev. 5.00 Jan 06, 2006 page 572 of 818
REJ09B0273-0500