SH7050 Datasheet, PDF (565/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Bit 6:
SWE
0
1
Description
Writes disabled
Writes enabled
[Setting condition]
When FWE = 1
Section 18 ROM (128 kB Version)
(Initial value)
Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU,
EV, PV, E, or P bit at the same time.
Bit 5:
ESU
0
1
Description
Erase setup cleared
Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the
SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 4:
PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE,
ESU, PSU, PV, E, or P bit at the same time.
Bit 3:
EV
0
1
Description
Erase-verify mode cleared
Transition to erase-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
(Initial value)
Rev. 5.00 Jan 06, 2006 page 545 of 818
REJ09B0273-0500