SH7050 Datasheet, PDF (530/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 16 Pin Function Controller (PFC)
16.3.13 Port G IO Register (PGIOR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG1 PG1 PG1 PG1 PG1 PG1 PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
5 4 3 2 1 0 IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
IOR IOR IOR IOR IOR IOR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port G IO register (PGIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port G. Bits PG15IOR to PG0IOR correspond to pins
PG15/IRQ5/TIOB5 to PG0/ADTRG/IRQOUT. PGIOR is enabled when port G pins function as
general input/output pins (PG15 to PG0), serial clock pins (SCK1, SCK0), or timer input/output
pins (TIOD3, TIOA4, TIOB4, TIOC4, TIOD4, TIOA5, TIOB5), and is disabled otherwise.
When port G pins function as PG15 to PG0, SCK1 and SCK0, or TIOD3, TIOA4, TIOB4, TIOC4,
TIOD4, TIOA5, and TIOB5, a pin becomes an output when the corresponding bit in PGIOR is set
to 1, and an input when the bit is cleared to 0.
PGIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.14 Port G Control Registers 1 and 2 (PGCR1, PGCR2)
Port G control registers 1 and 2 (PGCR1, PGCR2) are 16-bit readable/writable registers that select
the functions of the 16 multiplex pins in port G. PGCR1 selects the functions of the pins for the
upper 8 bits in port G, and PGCR2 selects the functions of the pins for the lower 8 bits in port G.
PGCR1 and PGCR2 are initialized to H'0AAA and H'AA80, respectively, by a power-on reset
(excluding a WDT power-on reset), and in hardware standby mode. They are not initialized in
software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 510 of 818
REJ09B0273-0500