SH7050 Datasheet, PDF (472/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
14.4.3 Analog Input Setting and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit in A/D0 and A/D1. The A/D converter
samples the analog input at time t_D (A/D conversion start delay time) after the ADST bit is set to 1,
then starts conversion. Figure 14.5 shows the A/D conversion timing.
The A/D conversion time (t_CONV) includes t_D and the analog input sampling time (t_SPL). The length of
t_D is not fixed, since it includes the time required for synchronization of the A/D conversion
operation. The total conversion time therefore varies within the ranges shown in table 14.4.
In scan mode, the t_CONV values given in table 14.4 apply to the first conversion. In the second and
subsequent conversions, t_CONV is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
Table 14.4 A/D Conversion Time (Single Mode)
Item
A/D conversion start
delay time
Input sampling time
(A/D0)
Input sampling time
(A/D1)
A/D conversion time
Symbol Min
t
10
D
CKS = 0
Typ Max
— 17
t_SPL
— 64 —
t_SPL
— 64 —
t_CONV
259 — 266
CKS = 1
Min Typ Max
6
—9
— 32 —
— 32 —
131 — 134
Unit
States
Rev. 5.00 Jan 06, 2006 page 452 of 818
REJ09B0273-0500