SH7050 Datasheet, PDF (436/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.17 is a sample flowchart for initializing the SCI.
1. Write the value corresponding to the bit rate in the bit rate register (BRR) unless an external
clock is used.
2. Select the clock source in the serial control register (SCR). Leave RIE, TIE, TEIE, MPIE, TE,
and RE cleared to 0.
3. Select the communication format in the serial mode register (SMR).
4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the
serial control register (SCR) to 1. When selecting the simultaneous transmission and receiving,
set TE and RE bits to 1 simultaneously. Also set RIE, TIE, TEIE, and MPIE. The TxD, RxD
pins becomes usable in response to the PFC corresponding bits and the TE, RE bit settings.
Start of initialization
Clear TE and RE bits to 0 in SCR
Set RIE, TIE, TEIE, MPIE, CKE1,
and CKE0 bits in SCR
1
(TE and RE are 0)
Select transmit/receive
format in SMR
2
Set value in BRR
3
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE to 1 in SCR;
Set RIE, TIE, TEIE, and MPIE bits ⁴
End
Figure 13.17 Sample Flowchart for SCI Initialization
Rev. 5.00 Jan 06, 2006 page 416 of 818
REJ09B0273-0500