SH7050 Datasheet, PDF (113/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
1
3
5 + m1 + m2 + m3
3 m1 m2 1 m3 1
IRQ
Instruction (instruction
replaced by interrupt
exception processing)
Overrun fetch
Interrupt service routine
start instruction
F DE E MMEME E
F
FDE
F: Instruction fetch (instruction fetched from memory where program is stored).
D: Instruction decoding (fetched instruction is decoded).
E: Instruction execution (data operation and address calculation is performed
according to the results of decoding).
M: Memory access (data in memory is accessed).
Figure 6.5 Pipeline when an IRQ Interrupt is Accepted
6.6 Data Transfer with Interrupt Request Signals
The following data transfers can be done using interrupt request signals:
• Activate DMAC only, without generating CPU interrupt
Among interrupt sources, those designated as DMAC activating sources are masked and not input
to the INTC. The masking condition is listed below:
Mask condition = DME • (DE0 • source selection 0 + DE1 × source selection 1 + DE2 •
source selection 2 + DE3 • source selection 3)
Figure 6.6 is a block diagram of interrupt controller.
Rev. 5.00 Jan 06, 2006 page 93 of 818
REJ09B0273-0500