SH7050 Datasheet, PDF (375/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
12.1 Overview
The watchdog timer (WDT) is a 1-channel timer for monitoring system operations. If a system
encounters a problem (crashes, for example) and the timer counter overflows without being
rewritten correctly by the CPU, an overflow signal (WDTOVF) is output externally. The WDT
can simultaneously generate an internal reset signal for the entire chip.
When the watchdog function is not needed, the WDT can be used as an interval timer. In the
interval timer operation, an interval timer interrupt is generated at each counter overflow. The
WDT is also used in recovering from the standby mode.
12.1.1 Features
• Works in watchdog timer mode or interval timer mode.
• Outputs WDTOVF in the watchdog timer mode. When the counter overflows in the watchdog
timer mode, overflow signal WDTOVF is output externally. You can select whether to reset
the chip internally when this happens. Either the power-on reset or manual reset signal can be
selected as the internal reset signal.
• Generates interrupts in the interval timer mode. When the counter overflows, it generates an
interval timer interrupt.
• Clears standby mode.
• Works with eight counter input clocks.
Rev. 5.00 Jan 06, 2006 page 355 of 818
REJ09B0273-0500