SH7050 Datasheet, PDF (255/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.2.7 Timer Status Registers (TSR)
The timer status registers (TSR) are 8-bit registers. The ATU has eight TSR registers: two for
channel 0, one each for channels 1 and 2, two for channels 3 to 5, one for channels 6 to 9, and one
for channel 10.
Channel
0
1
2
3
4
5
6
7
8
9
10
Abbreviation
TSRAH, TSRAL
TSRB
TSRC
TSRDH, TSRDL
Function
Indicates input capture, interval interrupt, and overflow status.
Indicates input capture, compare-match, and overflow status
Indicates input capture, compare-match, and overflow status.
TSRE
Indicates cycle register compare-match status
TSRF
Indicates down-counter underflow status.
The TSR registers are 8-bit readable/writable registers containing flags that indicate free-running
counter (TCNT) overflow, channel 0 input capture or interval interrupt generation, general register
input capture or compare-match, channel 6 to 9 compare-matches, down-counter underflow.
Each flag is an interrupt source, and issues an interrupt request to the CPU if the interrupt is
enabled by the corresponding bit in the timer interrupt enable register (TIER).
Each TSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 235 of 818
REJ09B0273-0500