SH7050 Datasheet, PDF (342/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Offset One-Shot Pulse Output: An example of the setup
procedure for offset one-shot pulse output is shown in figure 10.49.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1), and select the second-stage
counter clock φ" with the CKSEL bit in the timer control register (TCR1, TCR2, TCR10).
2. Set the port C control register (PCCR) corresponding to the waveform output port to ATU one-
shot pulse output. Also set the corresponding bit to 1 in the port C IO register (PCIOR) to
specify the output attribute.
3. Set the one-shot pulse width in the down-counter (DCNT) corresponding to the port set in (2).
If necessary, an interrupt request can be sent to the CPU when the down-counter underflows by
making the appropriate setting in the interrupt enable register (TIERF).
4. Set the offset width in the channel 1 or 2 general register (GR1A–GR1F, GR2A, GR2B)
connected to the down-counter (DCNT) corresponding to the port set in (2).
5. Set the CN10A–CN10H bit in the timer connection register (TCNR) corresponding to the port
set in (2) to 1.
6. Set the corresponding bit to 1 in the timer start register (TSTR) to start the channel 1 or 2 free-
running counter (TCNT1, TCNT2). When the TCNT value and GR value match, the
corresponding DCNT starts counting down, and one-shot pulse output is performed.
Rev. 5.00 Jan 06, 2006 page 322 of 818
REJ09B0273-0500