SH7050 Datasheet, PDF (221/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 0: Figure 10.2 shows a block diagram of ATU channel 0.
TSTR
φ/m
1 ≤ m ≤ 32
Clock
selection
TGSR control
IRQER control
Control logic
OVI0
ITV
ICI0A
ICI0B
ICI0C
ICI0D
TIA0
TIB0
TIC0
TID0
TRG1A
Module data bus
Legend:
TSTR: Timer start register (16 bits)
TIOR0A: Timer I/O control register 0A (8 bits)
TGSR: Trigger selection register (8 bits)
TSRA: Timer status register A (8 bits)
TIERA: Timer interrupt enable register A (8 bits)
ITVRR: Interval interrupt request register (8 bits)
TCNT0: Free-running counter 0 (16 bits)
ICR0: Input capture register 0 (16 bits)
Interrupts:
OVI0: Overflow interrupt 0
ITV:
Interval interrupt
ICI0: Input capture interrupt 0
Inter-channel connection signal:
TRG1A: Channel 1/GR1A compare-match signal
Figure 10.2 Block Diagram of Channel 0
Rev. 5.00 Jan 06, 2006 page 201 of 818
REJ09B0273-0500