SH7050 Datasheet, PDF (308/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.3.4 Input Capture Function
In ATU channels 0 to 5, when input capture is specified for the timer I/O control register (TIOR),
an input capture trigger signal is input from the corresponding external pin (TIA0 to TID0, TIOA1
to TIOF1, TIOA2, TIOB2, TIOA3 to TIOD3, TIO4A to TIOD4, TIOA5, TIOB5). A free-running
counter (TCNT) starts counting up when 1 is set in the timer start register (TSTR). When a trigger
signal is input from one of the above external pins, the counter value is transferred to the
corresponding register (ICR0AH/L to ICR0DH/L, OSBR, GR1A to GR1F, GR2A, GR2B, GR3A
to GR3D, GR4A to GR4D, GR5A, GR5B).
The detected edge of the external trigger input data can be selected by making a setting in the
timer I/O control register (TIOR). Rising-edge, falling-edge, or both-edge detection can be
selected. A CPU interrupt request can be issued if the appropriate setting is made in the interrupt
enable register (TIER).
An example of free-running counter and input capture operation is shown in figure 10.14.
In the example in figure 10.14, ATU channel 1 is activated, and input capture operation is
performed with rising-edge detection specified for TIOA1 and both-edge detection for TIOB1.
Counter value
TCNT1 H'FFFF
Data 1
Data 2
Data 3
Data 4
H'0000
(32 bits in case of channel 0)
Time
STR1
TIOA1
TIOB1
GR1A
GR1B
H'FFFF
(32 bits in case of channel 0)
H'FFFF
(32 bits in case of channel 0)
Data 1
Data 3
Data 2
Data 4
Figure 10.14 Example of Input Capture Operation
Rev. 5.00 Jan 06, 2006 page 288 of 818
REJ09B0273-0500