SH7050 Datasheet, PDF (722/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register DH
(TSRDH)
H'FFFF8203
8
ATU
(Channels 3 to 5)
Bit: 7
6
5
4
Bit name: —
—
—
OVF3
Initial value: 0
0
0
0
R/W: R
R
R R/(W)*
Note: * Only 0 can be written to clear the flag.
3
IMF3D
0
R/(W)*
2
IMF3C
0
R/(W)*
1
IMF3B
0
R/(W)*
0
IMF3A
0
R/(W)*
Bit Bit Name
Value Description
4
Overflow flag
(OVF3)
0
[Clearing condition]
Read OVF3 when OVF3 =1, then write 0 in OVF3
(Initial value)
1
[Setting condition]
TCNT3 overflowed from H'FFFF to H'0000
3
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
Read IMF3D when IMF3D =1, then write 0 in IMF3D
(IMF3D)
1
[Setting conditions]
1. TCNT3 value is transferred to GR3D by an input capture signal
when GR3D functions as an input capture register
2. TCNT3 = GR3D when GR3D functions as an output compare
register
2
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF3C)
1
Read IMF3C when IMF3C =1, then write 0 in IMF3C
[Setting conditions]
1. TCNT3 value is transferred to GR3C by an input capture signal
when GR3C functions as an input capture register
2. TCNT3 = GR3C when GR3C functions as an output compare
register
1
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF3B)
1
Read IMF3B when IMF3B =1, then write 0 in IMF3B
[Setting conditions]
1. TCNT3 value is transferred to GR3B by an input capture signal
when GR3B functions as an input capture register
2. TCNT3 = GR3B when GR3B functions as an output compare
register
0
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF3A)
1
Read IMF3A when IMF3A =1, then write 0 in IMF3A
[Setting conditions]
1. TCNT3 value is transferred to GR3A by an input capture signal
when GR3A functions as an input capture register
2. TCNT3 = GR3A when GR3A functions as an output compare
register
Rev. 5.00 Jan 06, 2006 page 702 of 818
REJ09B0273-0500