SH7050 Datasheet, PDF(215/841 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

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SH7050 Datasheet, PDF (215/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

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Section 10 Advanced Timer Unit (ATU)

Section 10 Advanced Timer Unit (ATU)

10.1 Overview

The SH7050 series has an on-chip advanced timer unit (ATU) with one 32-bit timer channel and

nine 16-bit timer channels.

10.1.1 Features

ATU features are summarized below.

â¢ Capability to process up to 34 pulse inputs and outputs

â¢ Prescaler

ï£§ Input clock to channel 0 scaled in 1 stage, input clock to channels 1 to 9 scaled in 2 stages

ï£§ 1/1 to 1/32 clock scaling possible in initial stage for all channels

ï£§ 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 scaling possible in second stage for channels 1 to 10

ï£§ External clock TCLKA, TCLKB selection also possible for channels 1 to 5

â¢ Channel 0 has four 32-bit input capture lines, allowing the following operations:

ï£§ Rising-edge, falling-edge, or both-edge detection selectable

ï£§ Channel 1 compare-match can be used as capture signal (TRG1A) (ICR0A, ICR0D only)

ï£§ Interrupt can be generated by trigger input

ï£§ Interval interrupt generation function generates four interval interrupts as selected

â¢ Channels 1 and 2 have a total of eight 16-bit input capture/output compare registers and one

dedicated input capture register. The 16-bit output compare registers can also be selected for

channel 10 one-shot pulse offset.

ï£§ Waveform output by means of compare-match: Selection of 0 output, 1 output, or toggle

output

ï£§ Input capture function: Rising-edge, falling-edge, or both-edge detection

OSBR trigger source is channel 0 capture set to 1 (TRG0A)

ï£§ Eight counter overflow interrupts/compare-match interrupts/capture interrupts can be

generated (channel 1/AâF, channel 2/A, B)

ï£§ Compare-match signal (TRG1A) can be sent from channel 1 to channel 0 as a trigger

ï£§ Compare-match signal can be sent from channel 2 to the advanced pulse controller (APC)

â¢ Channels 3 to 5 have a total of ten 16-bit input capture/output compare/PWM registers (ten

inputs/outputs when using input capture/output compare, seven outputs when using PWM),

allowing the following operations:

ï£§ Selection of input capture, output compare, PWM mode

Rev. 5.00 Jan 06, 2006 page 195 of 818

REJ09B0273-0500

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