SH7050 Datasheet, PDF (276/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 1—Input Capture/Compare-Match Interrupt Enable (IME1B): Enables or disables
interrupt requests by IMF1B in TSR when IMF1B is set to 1.
Bit 1:
IME1B
0
1
Description
IMI1B interrupt requested by IMF1B is disabled
IMI1B interrupt requested by IMF1B is enabled
(Initial value)
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME1A): Enables or disables
interrupt requests by IMF1A in TSR when IMF1A is set to 1.
Bit 0:
IME1A
0
1
Description
IMI1A interrupt requested by IMF1A is disabled
IMI1A interrupt requested by IMF1A is enabled
(Initial value)
Timer Interrupt Enable Register C (TIERC)
TIERC controls enabling/disabling of channel 2 input capture, compare-match, and overflow
interrupt requests.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— OVE2 IME2B IME2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Overflow Interrupt Enable (OVE2): Enables or disables interrupt requests by OVF2 in
TSR when OVF2 is set to 1.
Bit 2:
OVE2
0
1
Description
OVI2 interrupt requested by OVF2 is disabled
OVI2 interrupt requested by OVF2 is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 256 of 818
REJ09B0273-0500