SH7050 Datasheet, PDF (448/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
16 clocks
8 clocks
Internal ⁰
base clock
78
15 0
78
–7.5 clocks +7.5 clocks
Receive
data (RxD)
Start bit
D0
15 0
5
D1
Synchronization
sampling timing
Data
sampling timing
Figure 13.23 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in the asynchronous mode can therefore be expressed as:
( ) ^{M = 0.5 − 1 − (L − 0.5) F − D − 0.5 (1 + F) × 100%}
2N
N
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0–1.0)
L : Frame length (L = 9–12)
F : Absolute deviation of clock frequency
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
D = 0.5, F = 0
M = (0.5 – 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
Rev. 5.00 Jan 06, 2006 page 428 of 818
REJ09B0273-0500