SH7050 Datasheet, PDF (317/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
In the example in figure 10.21, H'F000 is set in GR3D, H'F000 in GR3A, H'7000 in GR3B, and
H'0000 in GR3C, ATU channel 3 is activated, and waveform output is generated on external pins
TIOA3 to TIOD3.
H'FFFF
GR3D,
GR3A (H'F000)
GR3B (H'7000)
GR3C (H'0000)
Counter value
TCNT3
No change
Time
No change
TIOA3
TIOB3
TIOC3
Figure 10.21 Example of PWM Waveform Output Operation
10.3.10 Buffer Function
ATU channels 6 to 9 each have a free-running counter (TCNT6 to TCNT9), cycle register
(CYLR6 to CYLR9), duty register (DTR6 to DTR9), and buffer register (BFR6 to BFR9). PWM
waveform output by means of counter matches with the cycle register and duty register is
performed as described in section 10.3.9, PWM Timer Function. However, channels 6 to 9 also
include a buffer function, whereby the corresponding buffer register value is transferred to the
duty register on a match between the cycle register and counter. If the corresponding bit in timer
interrupt enable register E (TIERE) is set to 1, an interrupt request can be sent to the CPU when
the cycle register value and counter value match.
An example of buffered PWM operation is shown in figure 10.22.
In the example in figure 10.22, H'4000 is set in BFR6, H'A000 in DTR6, and H'F000 in CYLR6,
and after the PWM operation is started, the BFR6 value is changed to H'B000 and H'7000 during
Rev. 5.00 Jan 06, 2006 page 297 of 818
REJ09B0273-0500