SH7050 Datasheet, PDF (272/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 0—One-Shot Pulse Flag (OSF10A): Status flag that indicates a DCNT10A one-shot pulse.
Bit 0:
OSF10A
0
1
Description
[Clearing condition]
When OSF10A is read while set to 1, then 0 is written in OSF10A
[Setting condition]
When the down-counter (DCNT10A) value underflows
(Initial value)
10.2.8 Timer Interrupt Enable Registers (TIER)
The timer interrupt enable registers (TIER) are 8-bit registers. The ATU has seven TIER registers:
one each for channels 0, 1, and 2, two for channels 3 to 5, one for channels 6 to 9, and one for
channel 10.
Channel
0
Abbreviation
TIERA
1
TIERB
2
TIERC
3
TIERDH,
4
TIERDL
5
6
TIERE
7
8
9
10
TIERF
Function
Controls input capture, compare-match, and interval interrupt
request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
Controls cycle register compare-match interrupt request
enabling/disabling.
Controls underflow interrupt request enabling/disabling.
The TIER registers are 8-bit readable/writable registers that control enabling/disabling of free-
running counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests,
interval interrupt requests, general register and dedicated input capture register input
capture/compare-match interrupt requests, channel 6 to 9 compare-match interrupt requests, and
down-counter (DCNT) underflow interrupt requests.
Each TIER is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 252 of 818
REJ09B0273-0500