SH7050 Datasheet, PDF (635/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 19 ROM (256 kB Version)
19.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
19.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase
block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the
error-protected state. (See table 19.7.)
Table 19.7 Hardware Protection
Item
FWE pin protection
Reset/standby
protection
Description
• When a low level is input to the FWE pin,
FLMCR1, FLMCR2, EBR1, and EBR2 are
initialized, and the program/erase-
protected state is entered.
• In a reset (including a WDT overflow
reset) and in standby mode, FLMCR1,
FLMCR2, EBR1, and EBR2 are initialized,
and the program/erase-protected state is
entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section.
Functions
Program Erase
Yes
Yes
Yes
Yes
Rev. 5.00 Jan 06, 2006 page 615 of 818
REJ09B0273-0500