SH7050 Datasheet, PDF (95/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
6.1 Overview
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC has registers for setting the priority of each interrupt which can be
used by the user to order the priorities in which the interrupt requests are processed.
6.1.1 Features
The INTC has the following features:
• 16 levels of interrupt priority: By setting the eight interrupt-priority level registers, the
priorities of IRQ interrupts and on-chip peripheral module interrupts can be set in 16 levels for
different request sources.
• NMI noise canceler function: NMI input level bits indicate the NMI pin status. By reading
these bits with the interrupt exception service routine, the pin status can be confirmed, enabling
it to be used as a noise canceler.
• Notification of interrupt occurrence can be reported externally (IRQOUT pin). For example, it
is possible to request bus rights if an external bus master is informed that a peripheral module
interrupt has occurred when the LSI has released the bus rights.
Rev. 5.00 Jan 06, 2006 page 75 of 818
REJ09B0273-0500