SH7050 Datasheet, PDF (355/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between Interrupt Status Flag Clearing by DMAC and Setting by Input
Capture/Compare-Match: If a clear request signal is generated by the DMAC when the interrupt
status flag (ICF0B, CMF6) is set by input capture (ICR0B) or compare-match (CYLR6), clearing
by the DMAC has priority and the interrupt status flag is not set.
The width of the DMAC clear request signal is normally two states, the same as an ATU access
cycle, and clearing is performed in two states. If a bus wait, or a bus request from off-chip, occurs
while the DMAC clear request signal is being output, the DMAC clear request signal width will be
N states (N ≥ 3).
The timing in this case is shown in figure 10.59
a. When the input capture/compare-match signal precedes the interrupt status flag
clear signal by 1/2 state
CK
DMAC clear request
signal
Interrupt status flag
clear signal
Input capture/
compare-match signal
1/2 state
Interrupt status flag
ICF0B, CMF6
b. When the input capture/compare-match signal follows the interrupt status flag
clear signal by 1/2 state, and contention arises
CK
DMAC clear request
signal
Interrupt status flag
clear signal
Input capture/
compare-match signal
Interrupt status flag
ICF0B, CMF6
Figure 10.59 Contention between Interrupt Status Flag Clearing by DMAC and Setting by
Input Capture/Compare-Match
Rev. 5.00 Jan 06, 2006 page 335 of 818
REJ09B0273-0500