SH7050 Datasheet, PDF (337/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT) for the relevant channel.
Note:
When channel 0 input capture (ICR0A) occurs, the TCNT1 value is always transferred to
the offset base register (OSBR), irrespective of channel 1 free-running counter (TCNT1)
activation.
For details, see section 10.3.8, Twin-Capture Function.
Start
Select counter clock 1
Set port-ATU connection 2
Set input waveform edge
detection
3
Start counter
4
Input capture operation
Figure 10.45 Sample Setup Procedure for Input Capture
Rev. 5.00 Jan 06, 2006 page 317 of 818
REJ09B0273-0500