SH7050 Datasheet, PDF (563/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
18.4 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 18.2.
Table 18.2 Flash Memory Registers
Register Name
Abbreviation R/W Initial Value Address
Access Size
Flash memory control
register 1
FLMCR1
R/W^*1 H'00^*3
H'FFFF8580 8
Flash memory control
register 2
Erase block register 1
FLMCR2
EBR1
R^*2
H'00
R/W^*1 H'00^*4
H'FFFF8581 8
H'FFFF8582 8
RAM emulation register RAMER
R/W H'0000
H'FFFF8628 8, 16, 32
Notes: FLMCR1, FLMCR2, and EBR1 are 8-bit registers, and RAMER is a 16-bit register.
Only byte accesses are valid for FLMCR1, FLMCR2, and EBR1, the access requiring 3
cycles. Three cycles are required for a byte or word access to RAMER, and 6 cycles for a
longword access.
When a longword write is performed on RAMER, 0 must always be written to the lower
word (address H'FFFF8630). Operation is not guaranteed if any other value is written.
1. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid. Writes are also disabled when the FWE bit is set to 1 in FLMCR1.
2. A read in a mode in which on-chip flash memory is disabled will return H'00.
3. When a high level is input to the FWE pin, the initial value is H'80.
4. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
Rev. 5.00 Jan 06, 2006 page 543 of 818
REJ09B0273-0500