SH7050 Datasheet, PDF (379/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Description
Timer disabled: TCNT is initialized to H'00 and count-up stops (initial
value)
Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
Bits 4 and 3—Reserved: These bits always read as 1. The write value should always be 1.
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to the TCNT. The clock signals are obtained by dividing the frequency of the
system clock (φ).
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
Overflow Interval*
(φ = 20 MHz)
0
0
0
φ/2 (initial value)
25.6 µs
0
0
1
φ/64
819.2 µs
0
1
0
φ/128
1.6 ms
0
1
1
φ/256
3.3 ms
1
0
0
φ/512
6.6 ms
1
0
1
φ/1024
13.1 ms
1
1
0
φ/4096
52.4 ms
1
1
1
φ/8192
104.9 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00
until an overflow occurs.
Rev. 5.00 Jan 06, 2006 page 359 of 818
REJ09B0273-0500