SH7050 Datasheet, PDF (660/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 20 RAM
20.2 Operation
The on-chip RAM is controlled by means of the system control register (SYSCR).
When the RAME bit in SYSCR is set to 1, the on-chip RAM is enabled. Accesses to addresses
H'FFFFE800–H'FFFFFFFF (SH7050) and H'FFFFD800–H'FFFFFFFF (SH7051) are then directed
to the on-chip RAM.
When the RAME bit in SYSCR is cleared to 0, the on-chip RAM is not accessed. A read will
return an undefined value, and a write is invalid. If a transition is made to hardware standby mode
after the RAME bit in SYSCR is cleared to 0, the contents of the on-chip RAM are held.
For details of SYSCR, see 21.2.2, System Control Register (SYSCR), in section 21, Power-Down
State.
Rev. 5.00 Jan 06, 2006 page 640 of 818
REJ09B0273-0500