SH7050 Datasheet, PDF (745/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Interrupt Enable Register B
(TIERB)
H'FFFF82C4 (Channel 1) 8
ATU
Bit: 7
Bit name: —
Initial value: 0
R/W: R
6
OVE1
0
R/W
5
IME1F
0
R/W
4
IME1E
0
R/W
3
IME1D
0
R/W
2
IME1C
0
R/W
1
IME1B
0
R/W
0
IME1A
0
R/W
Bit
Bit Name
Value Description
6
Overflow interrupt enable 0
OVI1 interrupt requested by OVF1 flag is disabled
(OVE1)
(Initial value)
1
OVI1 interrupt requested by OVF1 flag is enabled
5
Input capture/compare 0
IMI1F interrupt requested by IMF1F flag is disabled
match interrupt enable
(Initial value)
(IME1F)
1
IMI1F interrupt requested by IMF1F flag is enabled
4
Input capture/compare 0
IMI1E interrupt requested by IMF1E flag is
match interrupt enable
disabled
(Initial value)
(IME1E)
1
IMI1E interrupt requested by IMF1E flag is enabled
3
Input capture/compare 0
IMI1D interrupt requested by IMF1D flag is
match interrupt enable
disabled
(Initial value)
(IME1D)
1
IMI1D interrupt requested by IMF1D flag is enabled
2
Input capture/compare 0
IMI1C interrupt requested by IMF1C flag is
match interrupt enable
disabled
(Initial value)
(IME1C)
1
IMI1C interrupt requested by IMF1C flag is enabled
1
Input capture/compare 0
IMI1B interrupt requested by IMF1B flag is
match interrupt enable
disabled
(Initial value)
(IME1B)
1
IMI1B interrupt requested by IMF1B flag is enabled
0
Input capture/compare 0
IMI1A interrupt requested by IMF1A flag is
match interrupt enable
disabled
(Initial value)
(IME1A)
1
IMI1A interrupt requested by IMF1A flag is enabled
Rev. 5.00 Jan 06, 2006 page 725 of 818
REJ09B0273-0500