SH7050 Datasheet, PDF (297/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.2.14 General Registers (GR)
The general registers (GR) are 16-bit registers. The ATU has 18 general registers: six in channel 1,
two in channel 2, four each in channels 3 and 4, and two in channel 5.
Channel
1
2
3
4
5
Abbreviation
GR1A, GR1B,
GR1C, GR1D,
GR1E, GR1F
GR2A, GR2B
GR3A, GR3B,
GR3C, GR3D
GR4A, GR4B,
GR4C, GR4D
GR5A, GR5B
Function
Dual-purpose input capture and output compare registers
General Registers 1A to 1F (GR1A to GR1F)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The GR registers are 16-bit readable/writable registers with both input capture and output compare
functions. Function switching is performed by means of the timer I/O control registers (TIOR).
When a general register is used for input capture, it stores the TCNT value on detection of an input
capture signal from an external source. The corresponding IMF bit in TSR is set to 1 at this time.
The input capture signal edge to be detected is specified by the corresponding TIOR.
When a general register is used for output compare, the GR value and free-running counter
(TCNT) value are constantly compared, and when both values match, the IMF bit in the timer
status register (TSR) is set to 1. Compare-match output is specified by the corresponding TIOR.
The GR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed by
a word read or write.
The GR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode and
software standby mode.
Rev. 5.00 Jan 06, 2006 page 277 of 818
REJ09B0273-0500