SH7050 Datasheet, PDF (202/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge
detection, DREQ sampling is conducted only on the first cycle.
In figure 9.23, DMAC transfer begins, at the earliest, three cycles after the timing of the first
sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the
TCR. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first
cycle only.
When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput
an edge request. The remaining transfer restarts after the first DRAK output.
The DACK output period in burst mode is the same as in cycle steal mode.
Rev. 5.00 Jan 06, 2006 page 182 of 818
REJ09B0273-0500