SH7050 Datasheet, PDF (22/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 1 Overview
Table 1.1 SH7050 Series Features
Item
CPU
Features
• Original Renesas architecture
• 32-bit internal architecture
• General register machine
 Sixteen 32-bit general registers
 Three 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set
 Fixed 16-bit instruction length for improved code efficiency
 Load-store architecture (basic operations are executed between
registers)
 Delayed unconditional/conditional branch instructions reduce pipeline
disruption during branches
 C-oriented instruction set
• Instruction execution time: Basic instructions execute in one state
(50 ns/instruction at 20 MHz operation)
• Address space: Architecture supports 4 Gbytes
• On-chip multiplier: Multiply operations (32 bits × 32 bits → 64 bits) and
multiply-and-accumulate operations (32 bits × 32 bits + 64 bits → 64 bits)
executed in two to four states
• Five-stage pipeline
Rev. 5.00 Jan 06, 2006 page 2 of 818
REJ09B0273-0500