SH7050 Datasheet, PDF (351/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between TCNT Write and Increment: If a write to a channel 0 to 9 free-running
counter (TCNT0 to TCNT9) is performed while that counter is counting up, the write to the
counter has priority and the counter is not incremented.
The timing in this case is shown in figure 10.55. In this example, the CPU writes H'5555 at the
point at which TCNT is to be incremented from H'1001 to H'1002.
T1
T2
CK
TCNT input clock
Address
TCNT address
Internal write signal
TCNT
1001
5555
(CPU write value)
5556
Figure 10.55 Contention between TCNT Write and Increment
Rev. 5.00 Jan 06, 2006 page 331 of 818
REJ09B0273-0500