SH7050 Datasheet, PDF (141/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

8.2.4 Wait Control Register 2 (WCR2)
Bit: 15
14
13
—
—
—
Initial value: 0
0
0
R/W: R
R
R
Section 8 Bus State Controller (BSC)
12
11
10
9
8
—
—
—
—
—
0
0
0
0
0
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
— DSW3 DSW2 DSW1 DSW0
Initial value: 0
0
0
0
1
1
1
1
R/W: R
R
R
R
R/W R/W R/W R/W
WCR2 is a 16-bit read/write register that specifies the number of access cycles for DRAM space
and CS space for DMA single address mode transfers.
Do not perform any DMA single address transfers before WCR2 is set.
WCR2 is initialized by a power-on reset and in hardware standby mode to H'000F. It is not
initialized by software standby mode.
Bits 15–4—Reserved: These bits always read as 0. The write value should always be 0.
Bits 3–0—CS Space DMA Single Address Mode Access Wait Specification (DSW3, DSW2,
DSW1, DSW0): Specifies the number of waits for CS space access (0–15) during DMA single
address mode accesses. These bits are independent of the W bits of the WCR1.
Bit 3:
DSW3
0
0
1
Bit 2:
DSW2
0
0
⋅⋅⋅
1
Bit 1:
DSW1
0
0
1
Bit 0:
DSW0
0
1
1
Description
No wait (external wait input disabled)
1 wait (external wait input enabled)
15 wait (external wait input enabled) (initial value)
Rev. 5.00 Jan 06, 2006 page 121 of 818
REJ09B0273-0500