SH7050 Datasheet, PDF (31/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 1 Overview
Type
Interrupts
Symbol
IRQOUT
Address bus A0–A21
Data bus
D0–D15
Bus control CS0–CS3
RD
WRH
WRL
WAIT
Direct memory DREQ0–
access
DREQ1
controller
(DMAC)
DRAK0–
DRAK1
DACK0–
DACK1
Pin No.
159
17–20, 22,
24–28, 30,
32–36, 38,
40–44
85–88, 90,
92–96, 98,
100–104
52–54, 133
50
46
45
48
131, 128
61, 62
129, 127
I/O
Output
Output
Input/
output
Output
Output
Output
Output
Input
Input
Output
Output
Name
Interrupt
request
output
Address bus
Function
Indicates that an interrupt has
been generated.
Enables interrupt generation
to be recognized in the bus-
released state.
Address output pins.
Data bus
16-bit bidirectional data bus
pins.
Chip select
0 to 3
Chip select signals for
external memory or devices.
Read
Indicates reading from an
external device.
Upper write
Indicates writing of the upper
8 bits of external data.
Lower write
Indicates writing of the lower
8 bits of external data.
Wait
Input for wait cycle insertion
in bus cycles during external
space access.
DMA transfer Input pin for external requests
request
for DMA transfer.
(channels 0, 1)
DREQ request These pins output the input
acknowledg- sampling acknowledgment for
ment (channels external requests for DMA
0, 1)
transfer.
DMA transfer These pins output a strobe to
strobe
the external I/O of external
(channels 0, 1) DMA transfer requests.
Rev. 5.00 Jan 06, 2006 page 11 of 818
REJ09B0273-0500