SH7050 Datasheet, PDF (321/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
phenomenon is due to the fact that the value is H'0000 when the free-running counter (TCNT3 to
TCNT5) is cleared.
The timing in this case is shown in figure 10.25. In this example, H'0005 is set as the cycle register
value and H'0000 as the duty register value, the actual cycle value is H'0006, and the actual duty
value is H'0001.
Actual cycle
TCNT ^{0000 0001 0002 0003 0004 0005 0000 0001 0002 0003 0004 0005 0000 0001 0002 0003}
TCNT input clock
Compare-match signal
(duty)
Compare-match signal
(cycle)
Counter clear signal
PWM output
Actual duty
Figure 10.25 Channel 3 to 5 PWM Output Waveform and Counter Operation
10.3.14 Channel 3 to 5 PWM Output Waveform Settings and Interrupt Handling Times
Since channels 3 to 5 have no function for rewriting a general register (GR) simultaneously with
compare-match occurrence (buffer function) in PWM mode or when the counter clear function is
set, it may not be possible to generate waveform output with a resolution that exceeds the time
required to rewrite GR after a compare-match.
Rev. 5.00 Jan 06, 2006 page 301 of 818
REJ09B0273-0500