SH7050 Datasheet, PDF (809/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
User Break Address Register L
(UBARL)
H'FFFF8602
8/16/32
UBC
Bit:
Bit name:
Initial value:
R/W:
15
UBA15
0
R/W
14
UBA14
0
R/W
13
UBA13
0
R/W
12
UBA12
0
R/W
11
UBA11
0
R/W
10
UBA10
0
R/W
9
UBA9
0
R/W
8
UBA8
0
R/W
Bit:
Bit name:
Initial value:
R/W:
7
UBA7
0
R/W
6
UBA6
0
R/W
5
UBA5
0
R/W
4
UBA4
0
R/W
3
UBA3
0
R/W
2
UBA2
0
R/W
1
UBA1
0
R/W
0
UBA0
0
R/W
Bit
15–0
Bit Name
User break address 15 to 0
(UBA15 to UBA0)
Description
Lower half (bits 15 to 0) of the address taken as
the break condition
User Break Address Mask Register H
(UBAMRH)
H'FFFF8604
8/16/32
UBC
Bit: 15
14
13
12
11
10
9
8
Bit name: UBM31 UBM30 UBM29 UBM28 UBM27 UBM26 UBM25 UBM24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: UBM23 UBM22 UBM21 UBM20 UBM19 UBM18 UBM17 UBM16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15–0
Bit Name
User break address mask 31 to 16
(UBM31 to UBM16)
Description
Specifies bits to be masked in break address set
in UBARH
Rev. 5.00 Jan 06, 2006 page 789 of 818
REJ09B0273-0500