SH7050 Datasheet, PDF (470/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
14.4.2 Scan Mode
Scan mode is useful for monitoring analog inputs in a group of one or more channels. Scan mode
is selected for A/D0 by setting the ADM1 and ADM0 bits in A/D control/status register 0
(ADSCR0) to 01 (4-channel scan mode), 10 8-channel scan mode), or 11 (12-channel scan mode),
and for A/D1 by setting the SCAN bit in A/D control/status register 1 (ADCSR1) to 1. When the
ADST bit is set to 1, A/D conversion is started in scan mode.
In scan mode, A/D conversion is performed in low-to-high analog input channel number order
(AN0, AN1 ... AN15). The ADST bit remains set to 1 until written with 0 by software.
When all conversions are completed within one selected analog group, the ADF flag in ADCSR is
set to 1 and A/D conversion us repeated. When ADF is set to 1, if the ADIE bit in ADCSR is also
1, an ADI interrupt (ADI0 or ADI1) is requested. To clear the ADF flag, first read ADF when set
to 1, then write 0 in ADF. If the DMAC is activated by the ADI interrupt, ADF is cleared
automatically.
An example of the operation when analog input channels 0 to 2 and 4 to 6 (AN0 to AN2 and AN4
to AN6) are selected and A/D conversion is performed in 8-channel scan mode is described in
Figure 14.4. Figure 14.6 shows a timing diagram for this example.
1. 8-channel scan mode is selected (ADM1 = 1, ADM0 = 0), input channels AN0 to AN2 and
AN4 to AN6 are selected (CH3 = 0, CH2 = 0, CH1 = 1, CH0 = 0), and A/D conversion is
started.
2. When conversion of the first channel (AN0) is completed, the result is transferred to ADDR0.
Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion is completed for all the channels (AN0 to AN2) in one selected analog group
(analog group 0), the ADF flag is set to 1. If the ADIE bit is also 1, an ADI interrupt is
requested.
5. Conversion of the fourth channel (AN4) starts automatically.
6. Conversion proceeds in the same way through the sixth channel (AN6)
7. Steps 2 to 6 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After this, if the ADST bit is set to 1, A/D conversion starts
again from the first channel (AN0).
Rev. 5.00 Jan 06, 2006 page 450 of 818
REJ09B0273-0500