SH7050 Datasheet, PDF (248/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timer I/O Control Registers 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A)
Timer I/O control register 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A) are 8-bit registers.
There are four TIOR registers, three for timer 1 and one for timer 2.
TIOR1A
Bit: 7
6
5
4
3
2
1
0
— IO1B2 IO1B1 IO1B0 — IO1A2 IO1A1 IO1A0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR1B
Bit: 7
6
5
4
3
2
1
0
— IO1D2 IO1D1 IO1D0 — IO1C2 IO1C1 IO1C0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR1C
Bit: 7
6
5
4
3
2
1
0
— IO1F2 IO1F1 IO1F0 — IO1E2 IO1E1 IO1E0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
Registers TIOR0A to TIOR1C specify whether general registers GR1A to GR1F are used as input
capture or compare-match registers, and also perform edge detection and output value setting.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR2A
Bit: 7
6
5
4
3
2
1
0
— IO2B2 IO2B1 IO2B0 — IO2A2 IO2A1 IO2A0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W
R
R/W R/W R/W
TIOR2A specifies whether general registers GR2A and GR2B are used as input capture or
compare-match registers, and also performs edge detection and output value setting.
Rev. 5.00 Jan 06, 2006 page 228 of 818
REJ09B0273-0500