SH7050 Datasheet, PDF (64/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
SUB
Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn–Rm → Rn,
Underflow → T
1
Overflow
Note: * The normal minimum number of execution cycles. (The number in parentheses is the
number of cycles when there is contention with following instructions.)
Table 2.14 Logic Operation Instructions
Instruction
Instruction Code
Operation
Execu-
tion
Cycles T Bit
AND Rm,Rn
0010nnnnmmmm1001 Rn & Rm → Rn
1
—
AND #imm,R0
11001001iiiiiiii R0 & imm → R0
1
—
AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm → 3
—
(R0 + GBR)
NOT Rm,Rn
0110nnnnmmmm0111 ~Rm → Rn
1
—
OR Rm,Rn
0010nnnnmmmm1011 Rn | Rm → Rn
1
—
OR #imm,R0
11001011iiiiiiii R0 | imm → R0
1
—
OR.B #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm →
3
—
(R0 + GBR)
TAS.B @Rn
0100nnnn00011011 If (Rn) is 0, 1 → T; 1 → 4
MSB of (Rn)^*
Test
result
TST Rm,Rn
0010nnnnmmmm1000 Rn & Rm; if the result is 1
0, 1 → T
Test
result
TST #imm,R0
11001000iiiiiiii R0 & imm; if the result is 1
0, 1 → T
Test
result
TST.B #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if 3
the result is 0, 1 → T
Test
result
XOR Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm → Rn
1
—
XOR #imm,R0
11001010iiiiiiii R0 ^ imm → R0
1
—
XOR.B #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm → 3
—
(R0 + GBR)
Note: * The on-chip DMAC bus cycles are not inserted between the read and write cycles of
TAS instruction execution. However, bus release due to BREQ is carried out.
Rev. 5.00 Jan 06, 2006 page 44 of 818
REJ09B0273-0500