SH7050 Datasheet, PDF (368/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 11 Advanced Pulse Controller (APC)
11.2 Register Descriptions
11.2.1 Pulse Output Port Control Register (POPCR)
The pulse output port control register (POPCR) is a 16-bit readable/writable register.
POPCR is initialized to H'0000 by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0 PULS7 PULS6 PULS5 PULS4 PULS3 PULS2 PULS1 PULS0
ROE ROE ROE ROE ROE ROE ROE ROE SOE SOE SOE SOE SOE SOE SOE SOE
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 8—PULS7 to PULS0 Reset Output Enable (PULS7ROE to PULS0ROE): These
bits enable or disable 0 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 15 to 8:
PULS7 to 0ROE
0
1
Description
0 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
0 output to APC pulse output pin (PULS7–PULS0) is enabled
When one of these bits is set to 1, 0 is output from the corresponding pin on a compare-match
between the GR2B and TCNT2 values.
Bits 7 to 0—PULS7 to PULS0 Set Output Enable (PULS7SOE to PULS0SOE): These bits
enable or disable 1 output to the APC pulse output pins (PULS7 to PULS0) bit by bit.
Bits 7 to 0:
PULS7 to 0SOE
0
1
Description
1 output to APC pulse output pin (PULS7–PULS0) is disabled (Initial value)
1 output to APC pulse output pin (PULS7–PULS0) is enabled
When one of these bits is set to 1, 1 is output from the corresponding pin on a compare-match
between the GR2A and TCNT2 values.
Rev. 5.00 Jan 06, 2006 page 348 of 818
REJ09B0273-0500