SH7050 Datasheet, PDF (173/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request Mode: In this mode a transfer is performed at the transfer
request signal (interrupt request signal) of an on-chip peripheral module. As indicated in table 9.4,
there are ten transfer request signals: five from the multifunction timer pulse unit (MTU), which
are compare match or input capture interrupts; the receive data full interrupts (RxI) and transmit
data empty interrupts (TxI) of the two serial communication interfaces (SCI); and the A/D
conversion end interrupt (ADI) of the A/D converter. When DMA transfers are enabled (DE = 1,
DME = 1, TE = 0, NMIF = 0, AE = 0), a transfer is performed upon the input of a transfer request
signal.
The transfer request source need not be the data transfer source or transfer destination. However,
when the transfer request is set by RxI (transfer request because SCI’s receive data is full), the
transfer source must be the SCI’s receive data register (RDR). When the transfer request is set by
TxI (transfer request because SCI’s transmit data is empty), the transfer destination must be the
SCI’s transmit data register (TDR). Also, if the transfer request is set to the A/D converter, the
data transfer destination must be the A/D converter register.
Rev. 5.00 Jan 06, 2006 page 153 of 818
REJ09B0273-0500