SH7050 Datasheet, PDF (331/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.4.2 Interrupt Status Flag Clearing
Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag
after reading it while set to 1.
The procedure and timing in this case are shown in figure 10.35.
Start
Read 1 from TSR
CK
Address
TSR write cycle
T1
T2
TSR address
Write 0 to TSR
Internal write
signal
Interrupt status flag
Interrupt status
flag cleared
IMF, ICF, CMF,
OVF, OSF, IIF
Interrupt request
signal
Figure 10.35 Procedure and Timing for Clearing by CPU Program
Rev. 5.00 Jan 06, 2006 page 311 of 818
REJ09B0273-0500